Register | Bits | Description |
---|---|---|
D | 8 | Data Register |
DF | 1 | Data Flag (carry/borrow) |
R(0-f) | 16 | General Registers |
P | 4 | Specifies which R register is program counter |
X | 4 | Specifies which R register is data pointer |
I | 4 | High nybble of instruction byte, not directly accessable |
N | 4 | Low nybble of instruction byte, not directly accessable |
T | 8 | Holds X and P during interrupt, X is high nybble, not directly accessable |
IE | 1 | Interrupt Enable |
Q | 1 | Output Flip/Flop |
Opcode | Mnemonic | Instruction | Operation |
---|---|---|---|
0N | LDN | Load via N | M(R(N))->D; For N not 0 |
4N | LDA | Load Advance | M(R(N))->D; R(N)+1->R(N) |
F0 | LDX | Load via X | M(R(X))->D |
72 | LDXA | Load via X and advance | M(R(X))->D; R(X)+1->R(X) |
F8 | LDI | Load immediate | M(R(P))->D; R(P)+1->R(P) |
5N | STR | Store via N | D->M(R(N)) |
73 | STXD | Store Via X and dec. | D->M(R(X)); R(X)-1->R(X) |
1N | INC | Increment reg N | R(N)+1->R(N) |
2N | DEC | Decrement reg N | R(N)-1->R(N) |
60 | IRX | Increment reg X | R(X)+1->R(X) |
8N | GLO | Get low reg N | R(N).0->D |
AN | PLO | Put low reg N | D->R(N).0 |
9N | GHI | Get high reg N | R(N).1->D |
BN | PHI | Put high reg N | D->R(N).1 |
F1 | OR | Or | M(R(X)) or D->D |
F9 | ORI | Or immediate | M(R(P)) or D->D; R(P)+1->R(P) |
F3 | XOR | Exclusive or | M(R(X)) xor D->D |
FB | XRI | Exclusive or immediate | M(R(P)) xor D->D; R(P)+1->R(P) |
F2 | AND | And | M(R(X)) and D->D |
FA | ANI | And immediate | M(R(P)) and D->D; R(P)+1->R(P) |
F6 | SHR | Shift right | Shift D right; lsb(D)->DF; 0->msb(D) |
76 | SHRC | Shift right with carry | Shift D right; lsb(D)->DF; DF->msb(D) |
FE | SHL | Shift left | Shift D left; msb(D)->DF; 0->lsb(D) |
7E | SHLC | Shift left with carry | Shift D left; msb(D)->DF; DF->lsb(D) |
F4 | ADD | Add | M(R(X))+D->DF,D |
FC | ADI | Add immediate | M(R(P))+D->DF,D; R(P)+1->R(P) |
74 | ADC | Add with carry | M(R(X))+D+DF->DF,D |
7C | ADCI | Add with carry imm. | M(R(P))+D+DF->DF,D; R(P)+1->R(P) |
F5 | SD | Subtract D | M(R(X))-D->DF,D |
FD | SDI | Subtract D immediate | M(R(P))-D->DF,D; R(P)+1->R(P) |
75 | SDB | Sub. D with borrow | M(R(X))-D-DF->DF,D |
7D | SDBI | Sub. D with borrow imm. | M(R(P))-D-DF->DF,D; R(P)+1->R(P) |
F7 | SM | Subtract memory | D-M(R(X))->DF,D |
FF | SMI | Subtract Mem. imm. | D-M(R(P))->DF,D; R(P)+1->R(P) |
77 | SMB | Sub. Mem. with borrow | D-M(R(X))-DF->DF,D; |
7F | SMBI | Sub. Mem. w/borrow imm. | D-M(R(P))-DF->DF,D; R(P)+1>R(P) |
30 | BR | Branch | M(R(P))->R(P).0 |
38 | NBR | No Branch | R(P)+1->R(P) |
32 | BZ | Branch if D=0 | If D=0, M(R(P))->R(P).0 else R(P)+1->R(P) |
3A | BNZ | Branch if D<>0 | If D<>0, M(R(P))->R(P).0 else R(P)+1->R(P) |
33 | BDF | Branch if DF=1 | if DF=1, M(R(P))->R(P).0 else R(P)+1->R(P) |
3B | BNF | Branch if DF=0 | if DF=0, M(R(P))->R(P).0 else R(P)+1->R(P) |
31 | BQ | Branch if Q=1 | if Q=1, M(R(P))->R(P).0 else R(P)+1->R(P) |
39 | BNQ | Branch if Q=0 | if Q=0, M(R(P))->R(P).0 else R(P)+1->R(P) |
34 | B1 | Branch if EF1=1 | if EF1=1, M(R(P))->R(P).0 else R(P)+1->R(P) |
3C | BN1 | Branch if EF1=0 | if EF1=0, M(R(P))->R(P).0 else R(P)+1->R(P) |
35 | B2 | Branch if EF2=1 | if EF2=1, M(R(P))->R(P).0 else R(P)+1->R(P) |
3D | BN2 | Branch if EF2=0 | if EF2=0, M(R(P))->R(P).0 else R(P)+1->R(P) |
36 | B3 | Branch if EF3=1 | if EF3=1, M(R(P))->R(P).0 else R(P)+1->R(P) |
3E | BN3 | Branch if EF3=0 | if EF3=0, M(R(P))->R(P).0 else R(P)+1->R(P) |
37 | B4 | Branch if EF4=1 | if EF4=1, M(R(P))->R(P).0 else R(P)+1->R(P) |
3F | BN4 | Branch if EF4=0 | if EF4=0, M(R(P))->R(P).0 |
C0 | LBR | Long Branch | M(R(P))->R(P).1; M(R(P)+1)->R(P).0 |
C8 | NLBR | No long branch | R(P)+2->R(P) |
C2 | LBZ | Branch if D=0 | if D=0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P) |
CA | LBNZ | Branch if D<>0 | if D<>0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P) |
C3 | LBDF | Branch if DF=1 | if DF=1 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P) |
CB | LBNF | Branch if DF=0 | if DF=0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P) |
C1 | LBQ | Branch if Q=1 | if Q=1 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P) |
C9 | LBNQ | Branch if Q=0 | if Q=0 then M(R(P))->R(P).1; M(R(P)+1)->R(P).0 else R(P)+2->R(P) |
CE | LSZ | Skip if D=0 | if D=0, R(P)+2->R(P) else Continue |
C6 | LSNZ | Skip if D<>0 | if D<>0, R(P)+2->R(P) else Continue |
CF | LSDF | Skip if DF=1 | if DF=1, R(P)+2->R(P) else Continue |
C7 | LSNF | Skip if DF=0 | if DF=0, R(P)+2->R(P) else Continue |
CD | LSQ | Skip if Q=1 | if Q=1, R(P)+2->R(P) else Continue |
C5 | LSNQ | Skip if Q=0 | if Q=0, R(P)+2->R(P) else Continue |
CC | LSIE | Skip if IE=1 | if IE=0, R(P)+2->R(P) else Continue |
00 | IDL | Idle | Wait for DMA or Interrupt M(R(0))->Bus |
C4 | NOP | No operation | Continue |
DN | SEP | Set P | N->P |
EN | SEX | Set X | N->X |
7B | SEQ | Set Q | 1->Q |
7A | REQ | Reset Q | 0->Q |
78 | SAV | Save | T->M(R(X)) |
79 | MARK | Push X,P to stack | (X,P)->T; (X,P)->M(R(2)) then P->X; R(2)-1->R(2) |
70 | RET | Return | M(R(X))->(X,P); R(X)+1->R(X); 1->IE |
71 | DIS | Disable | M(R(X))->(X,P); R(X)+1->R(X); 0->IE |
61 | OUT1 | Output 1 | M(R(X))->Bus; R(X)+1->R(X); Nlines=1 |
62 | OUT1 | Output 2 | M(R(X))->Bus; R(X)+1->R(X); Nlines=2 |
63 | OUT1 | Output 3 | M(R(X))->Bus; R(X)+1->R(X); Nlines=3 |
64 | OUT1 | Output 4 | M(R(X))->Bus; R(X)+1->R(X); Nlines=4 |
65 | OUT1 | Output 5 | M(R(X))->Bus; R(X)+1->R(X); Nlines=5 |
66 | OUT1 | Output 6 | M(R(X))->Bus; R(X)+1->R(X); Nlines=6 |
67 | OUT1 | Output 7 | M(R(X))->Bus; R(X)+1->R(X); Nlines=7 |
69 | INP1 | Input 1 | Bus->M(R(X)); Bus->D; Nlines=1 |
6A | INP1 | Input 2 | Bus->M(R(X)); Bus->D; Nlines=2 |
6B | INP1 | Input 3 | Bus->M(R(X)); Bus->D; Nlines=3 |
6C | INP1 | Input 4 | Bus->M(R(X)); Bus->D; Nlines=4 |
6D | INP1 | Input 5 | Bus->M(R(X)); Bus->D; Nlines=5 |
6E | INP1 | Input 6 | Bus->M(R(X)); Bus->D; Nlines=6 |
6F | INP1 | Input 7 | Bus->M(R(X)); Bus->D; Nlines=7 |
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | A | B | C | D | E | F | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
0 | IDL | LDN 1 | LDN 2 | LDN 3 | LDN 4 | LDN 5 | LDN 6 | LDN 7 | LDN 8 | LDN 9 | LDN A | LDN B | LDN C | LDN D | LDN E | LDN F |
1 | INC 0 | INC 1 | INC 2 | INC 3 | INC 4 | INC 5 | INC 6 | INC 7 | INC 8 | INC 9 | INC A | INC B | INC C | INC D | INC E | INC F |
2 | DEC 0 | DEC 1 | DEC 2 | DEC 3 | DEC 4 | DEC 5 | DEC 6 | DEC 7 | DEC 8 | DEC 9 | DEC A | DEC B | DEC C | DEC D | DEC E | DEC F |
3 | BR | BQ | BZ | BDF | B1 | B2 | B3 | B4 | NBR | BNQ | BNZ | BNF | BN1 | BN2 | BN3 | BN4 |
4 | LDA 0 | LDA 1 | LDA 2 | LDA 3 | LDA 4 | LDA 5 | LDA 6 | LDA 7 | LDA 8 | LDA 9 | LDA A | LDA B | LDA C | LDA D | LDA E | LDA F |
5 | STR 0 | STR 1 | STR 2 | STR 3 | STR 4 | STR 5 | STR 6 | STR 7 | STR 8 | STR 9 | STR A | STR B | STR C | STR D | STR E | STR F |
6 | IRX | OUT 1 | OUT 2 | OUT 3 | OUT 4 | OUT 5 | OUT 6 | OUT 7 | --- | INP 1 | INP 2 | INP 3 | INP 4 | INP 5 | INP 6 | INP 7 |
7 | RET | DIS | LDXA | STXD | ADC | SDB | SHRC | SMB | SAV | MARK | REQ | SEQ | ADCI | SDBI | SHLC | SMBI |
8 | GLO 0 | GLO 1 | GLO 2 | GLO 3 | GLO 4 | GLO 5 | GLO 6 | GLO 7 | GLO 8 | GLO 9 | GLO A | GLO B | GLO C | GLO D | GLO E | GLO F |
9 | GHI 0 | GHI 1 | GHI 2 | GHI 3 | GHI 4 | GHI 5 | GHI 6 | GHI 7 | GHI 8 | GHI 9 | GHI A | GHI B | GHI C | GHI D | GHI E | GHI F |
A | PLO 0 | PLO 1 | PLO 2 | PLO 3 | PLO 4 | PLO 5 | PLO 6 | PLO 7 | PLO 8 | PLO 9 | PLO A | PLO B | PLO C | PLO D | PLO E | PLO F |
B | PHI 0 | PHI 1 | PHI 2 | PHI 3 | PHI 4 | PHI 5 | PHI 6 | PHI 7 | PHI 8 | PHI 9 | PHI A | PHI B | PHI C | PHI D | PHI E | PHI F |
C | LBR | LBQ | LBZ | LBDF | NOP | LSNQ | LSNZ | LSNF | NLBR | LBNQ | LBNZ | LBNF | LSIE | LSQ | LSZ | LSDF |
D | SEP 0 | SEP 1 | SEP 2 | SEP 3 | SEP 4 | SEP 5 | SEP 6 | SEP 7 | SEP 8 | SEP 9 | SEP A | SEP B | SEP C | SEP D | SEP E | SEP F |
E | SEX 0 | SEX 1 | SEX 2 | SEX 3 | SEX 4 | SEX 5 | SEX 6 | SEX 7 | SEX 8 | SEX 9 | SEX A | SEX B | SEX C | SEX D | SEX E | SEX F |
F | LDX | OR | AND | XOR | ADD | SD | SHR | SM | LDI | ORI | ANI | XRI | ADI | SDI | SHL | SMI |
1805 Extended Instructions:
Opcode | Mnemonic | Instruction | Operation |
---|---|---|---|
68 CN | RLDI | Register load immed. | M(R(P))->R(N).1; M(R(P)+1)->R(N).0; R(P)+2->R(P) |
68 6N | RLXA | Register load via X, Adv. | M(R(X))->R(N).1; M(R(X)+1)->R(N).0; R(X)+2->R(X) |
68 AN | RSXD | Register store via X, Dec. | R(N).0->M(R(X)); R(N).1->M(R(X)-1); R(X)-2->R(X) |
68 2N | DBNZ | Dec reg N, LBR if not 0 | R(N)-1->R(N); if R(N) not 0,M(R(P))->R(P).1;M(R(P)+1)->R(P).0 |
else R(P)+2->R(P) | |||
68 BN | RNX | Register N to X copy | R(N)->R(X) |
68 F4 | DADD | Decimal Add | M(R(X))+D->DF,D, decimal adjust |
68 FC | DADI | Decimal Add Immed. | M(R(P))+D->DF,D, decimal adjust; R(P)+1->R(P) |
68 74 | DADC | Decimal Add with carry | M(R(X))+D+DF->DF,D, decimal adjust |
68 7C | DACI | Decimal Add Immed. with carry | M(R(P))+D+DF->DF,D, decimal adjust; R(P)+1->R(P) |
68 F7 | DSM | Decimal sub memory | D-M(R(X))->DF,D, decimal adjust |
68 FF | DSMI | Decimal sub Immed | D-M(R(P))->DF,D, decimal adjust; R(P)+1->R(P) |
68 77 | DSMB | Decimal sub memory w/borrow | D-M(R(X))-(not DF)->DF,D, decimal adjust |
68 7F | DSBI | Decimal sub Immed w/borrow | D-M(R(P))-(not DF)->DF,D, decimal adjust; R(P)+1->R(P) |
68 3E | BCI | Short branch on counter int | if CI=1,M(R(P))->R(P).0; 0->CI |
else R(P)+1->R(P) | |||
68 3F | BXI | Short branch on external int | if XI=1,M(R(P))->R(P).0; 0->XI |
else R(P)+1->R(P) | |||
68 06 | LDC | Load counter | Cntr stopped:D->CH,CNTR;0->CI |
Cntr running:D->CH | |||
68 08 | GEC | Get counter | Cntr->D |
68 00 | STPC | Stop counter | Stop Cntr; 0->/32 prescaler |
68 01 | DTC | Decrement counter | Cntr-1->Cntr |
68 07 | STM | Set timer mode and start | TPA/32->Cntr |
68 05 | SCM1 | Set counter mode 1 and start | /EF1->Cntr clock |
68 03 | SCM2 | Set counter mode 2 and start | /EF2->Cntr clock |
68 04 | SPM1 | Set pulse width mode 1 and start | TPA.EF1>Cntr clock, /EF1 / stops count |
68 02 | SPM2 | Set pulse width mode 2 and start | TPA.EF2>Cntr clock, /EF2 / stops count |
68 09 | ETQ | Enable toggle Q | if Cntr=1; next Cntr clock / /Q->Q |
68 0A | XIE | External int enable | 1->XIE |
68 0B | XID | External int disable | 0->XIE |
68 0C | CIE | Counter int enable | 1->CIE |
68 0D | CID | Counter int disable | 0->CIE |
68 76 | DSAV | Save T,D,DF | R(X)-1->R(X); T->M(R(X)) |
R(X)-1->R(X); D->M(R(X)) | |||
Shift D right with carry | |||
R(X)-1->R(X); D->M(R(X)) | |||
68 8N | SCAL | Standard call | R(N).0->M(R(X)); R(N).1->M(R(X)-1) |
R(X)-2->R(X); R(P)->R(N) | |||
M(R(N))->R(P).1 | |||
M(R(N)+1)->R(P).0 | |||
R(N)+2->R(N) | |||
68 9N | SRET | Standard return | R(N)->R(P) |
M(R(X)+1)->R(N).1; M(R(X)+2)->R(N).0 | |||
R(X)+2->R(X) | |||
Reverse Opcode Table: 1805 extended (68) instructions
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
STPC
DTC
SPM2
SCM2
SPM1
SCM1
LDC
STM
GEC
ETQ
XIE
XID
CIE
CID
---
---
1
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
2
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
DBNZ
3
---
---
---
---
---
---
---
---
---
---
---
---
---
---
BCI
BXI
4
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
5
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
6
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
RLXA
7
---
---
---
---
DADC
---
DSAV
DSMB
---
---
---
---
DACI
---
---
DSBI
8
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
SCAL
9
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
SRET
A
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
RSXD
B
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
RNX
C
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
RLDI
D
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
E
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
---
F
---
---
---
---
DADD
---
---
DSM
---
---
---
---
DADI
---
---
DSMI